1. Field of the Invention
The present invention relates to a wiring modeling technique.
2. Description of the Prior Art
With increasingly higher degrees of integration and higher densities of semiconductor devices, the width of wirings formed on a semiconductor device chip and the spacing between adjacent wirings (hereinafter referred to as wiring spacing) have become finer and finer. Since such higher degrees of integration and higher densities and hence increased wiring capacities and wiring resistances have produced longer signal delays, it is essential to semiconductor device design to accurately estimate these signal delay factors.
In addition, as a result of such finer wirings, a discrepancy between a manufacturing aim for wiring cross-sectional profile and the cross-sectional profile of a wiring actually formed on a chip has an increased influence on the wiring capacitance and the wiring resistance. The term “manufacturing aim” used herein refers to making a wiring of rectangular cross-sectional profile, forming a wiring width according to a layout, and making the wiring thickness uniform throughout a chip. This discrepancy depends on and varies with the wiring width and the wiring spacing of that wiring, and a layout condition of other wirings around that wiring within a region where that wiring is formed.
When a conductor of much higher resistivity than a principal material of the wiring is partly used within the wiring, a wiring capacitance estimate depends on the surface shape of the wiring but a wiring resistance estimate depends on the cross-sectional profile of the wiring. In particular, when the wiring consists of a plurality of metal materials, the wiring resistance estimate would depend on the cross-sectional profile of a portion made of a principal metal material, and thus, the wiring capacitance and wiring resistance estimates should depend on different factors, respectively.
With prior wiring capacitance and wiring resistance estimation methods, however, on the assumption that all wirings are formed according to the manufacturing aim and also that the cross-sectional profile for wiring capacitance estimation is identical to that for wiring resistance estimation, the wiring capacitance and the wiring resistance would be calculated. Consequently, there may be an error between a signal delay actually occurring on a chip and a signal delay estimated from the calculated wiring capacitance and wiring resistance, resulting in a problem that the actual chip may not operate normally.
To solve these problems, it is essential in estimating the wiring capacitance and wiring resistance of each wiring actually formed on a chip to accurately reflect its cross-sectional profile which depends on the wiring width and the wiring spacing of that wiring, and the layout condition of other wirings around that wiring and which deviates from the manufacturing aim. In addition, it is necessary to separately calculate the cross-sectional profile for wiring capacitance estimation and the cross-sectional profile for wiring resistance estimation. In some cases, it may be necessary to correct the manufacturing aim itself with respect to the wiring width in advance during the mask design stage for correction of the above-mentioned error.